The present invention relates to technology for a semiconductor device.
Along with expanded device capacity, demand has increased in recent years for DRAM (Dynamic Random Access Memory) possessing higher speed, and low power consumption, so memory cell arrays are generally subdivided into subarrays and each subarray is controlled separately. Each of the subarrays are selected by main word lines extending along the row direction and column selection lines extending along the column direction. The memory cells within each subarray are arrayed in a matrix, and subword lines extend in the row direction and bit lines in the column direction. DRAM possessing this type of structure are called hierarchical DRAM and hierarchical DRAM are disclosed in the Japanese Unexamined Patent Application Publication No. 2001-273764, Japanese Unexamined Patent Application. Publication No. 2000-011639, and Japanese Unexamined Patent Application Publication No. 2001-243762.
This hierarchical DRAM requires a subword driver for driving the subword line. More specifically, a logic circuit is needed for inputting main word line signals and column select line signals. Moreover, each subarray includes a sense amplifier. Signals such as sense enable signal, a precharge signal, and bit line (Y switch select) signal are input to each sense amplifier. These signals are generated by logic circuits that input the column select line signals and signals of the main signal lines (main sense enable signal lines, main precharge signal lines, main bit select lines) that are arrayed parallel to the main word lines.